1. Field of the Invention
The present invention generally relates to electrodeposition process technology and, more particularly, to an electrodeposition process that yields uniform and planar deposits.
2. Description of Related Art
Conventional semiconductor devices generally include a semiconductor substrate, usually a silicon substrate, and a plurality of sequentially formed dielectric interlayers such as silicon dioxide and conductive paths or interconnects made of conductive materials. The interconnects are usually formed by filling a conductive material in trenches etched into the dielectric interlayers. In an integrated circuit, multiple levels of interconnect networks laterally extend with respect to the substrate surface. The interconnects formed in different layers can be electrically connected using vias or contacts. A conductive material filling process of such features, i.e., via openings, trenches, pads or contacts, can be carried out by depositing a conductive material over the substrate including such features. Excess conductive material on the substrate can then be removed using a planarization and polishing technique such as chemical mechanical polishing (CMP).
Copper (Cu) and Cu alloys have recently received considerable attention as interconnect materials because of their superior electromigration and low resistivity characteristics. The preferred method of Cu deposition is electrodeposition. During fabrication, copper is electroplated or electrodeposited on substrates that are previously coated with barrier and seed layers. Typical barrier materials generally include tungsten (W), tantalum (Ta), titanium (Ti), their alloys and their nitrides. A typical seed layer material for copper is usually a thin layer of copper that is CVD or PVD deposited on the aforementioned barrier layer.
There are many different designs of Cu plating systems. For example, U.S. Pat. No. 5,516,412 issued on May 14, 1996, to Andricacos et al. discloses a vertical paddle plating cell that is configured to electrodeposit a film on a flat article. U.S. Pat. No. 5,985,123 issued on Nov. 16, 1999, to Koon discloses yet another vertical electroplating apparatus, which purports to overcome the non-uniform deposition problems associated with varying substrate sizes.
During the Cu electrodeposition process, specially formulated plating solutions or electrolytes are used. These solutions or electrolytes contain ionic species of Cu and additives to control the texture, morphology, and the plating behavior of the deposited material. Additives are needed to make the deposited layers smooth and somewhat shiny.
There are many types of Cu plating solution formulations, some of which are commercially available. One such formulation includes Cu-sulfate (CuSO4) as the copper source (see James Kelly et al., Journal of The Electrochemical Society, Vol. 146, pages 2540-2545, (1999)) and includes water, sulfuric acid (H2SO4), and a small amount of chloride ions. As is well known, other chemicals, which are often referred to as additives, can be added to Cu plating solutions to achieve desired properties of the deposited material (e.g., see Robert Mikkola and Linlin Chen, “Investigation of the Roles of the Additive Components for Second Generation Copper Electroplating Chemistries used for Advanced Interconnect Metallization”, Proceedings of the International Interconnect Technology Conference, pages 117-119, Jun. 5-7, 2000).
FIGS. 1 through 2 exemplify a conventional electrodeposition method and apparatus. FIG. 1A illustrates a substrate 10 having an insulator layer 12 formed thereon. Using conventional etching techniques, features such as a row of small vias 14 and a wide trench 16 are formed on the insulator layer 12 and on the exposed regions of the substrate 10. In this example, the vias 14 are narrow and deep; in other words, they have high aspect ratios (i.e., their depth to width ratio is large). Typically, the widths of the vias 14 are sub-micronic. The trench 16 shown in this example, on the other hand, is wide and has a small aspect ratio. The width of the trench 16 may be five to fifty times or more greater than its depth.
FIGS. 1B-1C illustrate a conventional method for filling the features with copper material. FIG. 1B illustrates that a barrier/glue or adhesion layer 18 and a seed layer 20 are sequentially deposited on the substrate 10 and the insulator 12. The barrier layer 18 may be Ta, W, Ti, their alloys, their nitrides or combinations of them. The barrier layer 18 is generally deposited using any of the various sputtering methods, by chemical vapor deposition (CVD), or by electroless plating methods. Thereafter, the seed layer 20 is deposited over the barrier layer 18. The seed layer 20 is typically copper if the conductor to be plated is also copper and may be deposited on the barrier layer 18 using various sputtering methods, CVD, or electroless deposition or their combinations.
In FIG. 1C, after depositing the seed layer 20, a conductive material layer 22 (e.g., copper layer) is partially electrodeposited thereon from a suitable plating bath or bath formulation. During this step, an electrical contact is made to the copper seed layer 20 and/or the barrier layer 18 so that a cathodic (negative) voltage can be applied thereto with respect to an anode (not shown). Thereafter, the copper material layer 22 is electrodeposited over the substrate surface using plating solutions, as discussed above. By adjusting the amounts of the additives, such as the chloride ions, the suppressor/inhibitor, and the accelerator, it is possible to obtain bottom-up copper film growth in the small features.
As shown in FIG. 1C, the copper material 22 completely fills the via 14 and is generally conformal in the large trench 16, because the additives that are used are not operative in large features. For example, it is believed that the bottom up deposition into the via 14 occurs because the suppressor/inhibitor molecules attach themselves to the top of the via 14 to suppress the material growth thereabouts. These molecules can not effectively diffuse to the bottom surface of the via 14 through the narrow opening. Preferential adsorption of the accelerator on the bottom surface of the via 14 results in faster growth in that region, resulting in bottom-up growth and the Cu deposit profile as shown in FIG. 1C. Here, the Cu thickness that the bottom surface of the trench 16 is about the same as the Cu thickness t2 over the insulator layer 12.
As can be expected, to completely fill the trench 16 with the Cu material, further plating is required. FIG. 1D illustrates the resulting structure after additional Cu plating. In this case, the Cu thickness t3 over the insulator layer 12 is relatively large and there is a step S1 from the top of the Cu layer on the insulator layer 12 to the top of the Cu layer 22 in the trench 16. For integrated circuit (IC) applications, the Cu layer 22 needs to be subjected to CMP or some other material removal process so that the Cu layer 22 as well as the barrier layer 18 on the insulator layer 12 are removed, thereby leaving the Cu layer only within the features 14 and 16. These removal processes are known to be quite costly.
Methods and apparatus to achieve a generally planar Cu deposit as illustrated in FIG. 1E would be invaluable in terms of process efficiency and cost. The Cu thickness t5 over the insulator layer 12 in this example is smaller than the traditional case as shown in FIG. 1D, and the height of the step S2 is also much smaller. Removal of the thinner Cu layer in FIG. 1E by CMP or other methods would be easier, providing important cost savings.
In co-pending U.S. application Ser. No. 09/201,929, entitled “METHOD AND APPARATUS FOR ELECTROCHEMICAL MECHANICAL DEPOSITION”, filed Dec. 1, 1998 and commonly owned by the assignee of the present invention, a technique is disclosed that achieves deposition of the conductive material into the cavities on the substrate surface while minimizing deposition on the field regions by polishing the field regions with a pad as the conductive material is deposited, thus yielding planar copper deposits.
FIG. 2A shows a schematic depiction of a prior art electrodeposition system 30. In this system, a wafer 32 is held by a wafer holder 34 with the help of a ring clamp 36 covering the circumferential edge of the wafer 32. An electrical contact 38 is also shaped as a ring and connected to the (−) terminal of a power supply for cathodic plating. The wafer holder 34 is lowered into a plating cell 40 filled with plating electrolyte 42. An anode 44, which makes contact with the electrolyte 42, is placed across from the wafer surface and is connected to the (+) terminal of the power supply. The anode 44 may be made of the material to be deposited, i.e., copper, or of an appropriate inert anode material such as platinum, platinum coated titanium or graphite. A plating process commences upon application of power. In this plating system, the electrical contact 38 is sealed from the electrolyte and carries the plating current through the circumference of the wafer 32. However, the presence of the contact 38 and the clamp 36 at the circumference of the wafer 30 is an important drawback with this system and increases the edge exclusion indicated by ‘EE’ in FIG. 2A. As a result of edge exclusion, a very valuable prime area on the surface of the wafer 32 is lost.
FIGS. 1A through 1E show how the features on the wafer surface are filled with copper. For this filling process to be efficient and uniform throughout the wafer, it is important that a uniform thickness of copper be deposited over the whole wafer surface. Thickness uniformity needs to be very good because non-uniform copper thickness causes problems during the CMP process. As shown in FIG. 2B, in order to improve uniformity of the deposited layers, shields 46 may be included in prior art electroplating systems such as that shown in FIG. 2A. In such systems, either the wafer 32 or the shield 46 may be rotated. Such shields are described, for example, in U.S. Pat. No. 6,027,631 to Broadbent, U.S. Pat. No. 6,074,544 to Reid et al. and U.S. Pat. No. 6,103,085 to Woo et al.
In view of the foregoing, there is a need for alternative electrodeposition processes and systems which minimize edge exclusion problems and deposit uniform conductive films.